Embodiments described herein generally relate to power amplifiers, and more particularly relate to power amplifiers having improved power amplification by reduction of stress via even harmonic cancellation.
Unless otherwise indicated herein, the approaches described in the background section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in the background section.
Power amplifiers are generally configured to receive an AC signal, such as an RF signal, and boost the power of the AC signal. Traditional power amplifiers often include a single nMOS transistor or a cascode with tank loading. FIG. 1 is a simplified schematic of a traditional power amplifier 100 that includes an nMOS transistor 105 coupled between an inductor 110 and ground. Inductor 110 may be coupled to a voltage source Vdd. Inductor 110 may also be coupled to a capacitor 115 in a tank configuration for tuning the resonance of power amplifier 100. NMOS transistor 105 may be in a common source configuration with the gate of nMOS transistor 105 configured to operate as an input AC In to receive an AC signal and a drain coupled to the output Vout of power amplifier 100. FIG. 2 is a simplified schematic of another traditional power amplifier 200 that includes first and second nMOS transistors 205 and 210 in series between an inductor 215 and ground. Inductor 215 may be coupled to a voltage source Vdd. Inductor 215 may also be coupled to a capacitor 220 in a tank configuration for tuning the resonance of power amplifier 200. The nMOS transistors 205 and 210 may be in a common source, common gate configuration (i.e., a cascode configuration) with the gate of nMOS transistor 205 configured to operate as an input AC In to receive an AC signal and a drain of transistor 210 coupled to the output Vout of power amplifier 200.
In traditional power amplifiers, such as power amplifiers 100 and 200 described above, the typical maximum voltage at the output Vout is 2Vdd and the typical maximum power output is about (2Vdd)2/R where R is a load resistance of the power amplifiers. The typical maximum voltage output is limited by a number of factors including the stress across the transistors, such as the stress across nMOS transistor 205 and the stress across nMOS transistor 210. For example, if power amplifier 200 is configured for 2.5V operation, voltages of 2.7V and above across nMOS transistor 205 and nMOS transistor 210 with current running through nMOS transistors 205 and 210 causes stress, which negatively effects maximum amplification. Voltages of 2.7V and above across nMOS transistor 205 and nMOS transistor 210 may occur due to fundamental and higher order harmonics of the fundamental harmonic of a received AC signal.
While the power output of traditional power amplifiers, such as power amplifiers 100 and 200, is acceptable for a number of amplification, it would be desirable to provide new power amplifiers that provide higher power output than the power output of traditional power amplifiers via the reduction of stress.